The candidate will be required to perform IP integration and IP test/debug mode verification at the SoC level. This role involves creating RTL designs, performing linting, and executing CDC and RDC analysis for both RTL and gates.
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Job Title: PCB Hardware Design Engineer. Location: Allentown, PA, Fort Collins, CO, or San Jose, CA. A Hardware engineering position responsible for developing Bench and System Level Test PCBs for Broadcom products targeted at hyperscale data center applications.
We are seeking an experienced ASIC Emulation and Verification Engineer to bridge the gap between simulation and hardware acceleration.
ATE Test Engineer – XPU Yield, Quality, and RMA Debug.
Broadcom's ASIC Product Division is seeking candidates for a DFT Engineer position at our San Jose, California Development Center. The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up.
The candidate will be responsible for leading and executing Synthesis, Static Timing Analysis (STA), Formal Verification, and low-power implementation activities of Mixed Signal (MXS) blocks.
The CSG group at Broadcom has brought some of the most complex and cutting edge networking ASIC's and multichip solutions to market over the last decade. develops Tomahawk ASICs for Scale-Out and Scale-Up AI Networks.
Job Description: Kubernetes Platform infrastructure Architect.
Job Description: Kubernetes Platform infrastructure Architect.
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