The Principal System Architect is a senior technical individual contributor in the DRAM System and Component Architecture organization in charge of pathfinding and defining Micron’s DRAM future product architecture.
Develop and drive product strategy, roadmap planning, and requirements definition for next-generation HBM solutions targeting AI, HPC, and cloud infrastructure markets.
Research customer needs, market trends, and competitors. Use what you learn to define product priorities and guide decisions throughout development. Bring products to market. Lead work from concept through launch with engineering, sales, marketing, and other teams.
In the role of Principal Segment Development Manager, you will spearhead our marketing activities in Folsom, CA. This job holds a key role in crafting the direction for our memory and storage offerings, supporting our efforts to stay ahead of the competition.
Lead HBM enablement for strategic AI customers, aligning system requirements, qualification plans, development milestones, risks, and product readiness.
Design, implement, and debug complex RTL logic and integrate IP into larger subsystems. Support front-end design flow including lint, CDC, synthesis, and ECO activities. Collaborate with SOC design, verification, STA, and physical design teams to deliver high-quality silicon.
GenAI System Development: Design, build, and improve GenAI-powered and agentic systems supporting ASIC semiconductor engineering workflows such as code generation, data extraction, analytics, documentation automation, failure triage, root cause analysis, and technical knowledge…
MicronNew · 1d ago
Define clocking architectures, power sequencing, power delivery, and on-die signal interfaces. Define and analyze on-die power delivery networks (PDN) and full-chip thermal implications, including power hot-spot identification and mitigation.
Architect, design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Architect and design memory sub-systems including memory IP selection and integration, bus and protocol selection, and power/performance/area optimization.
Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects. Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging. Establish ESD/LUP standards, rule decks, and signoff criteria.
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