Translate architecture requirements into scalable microarchitectures and drive implementation from concept through silicon. Design, implement, and review SystemVerilog RTL for advanced memory system architectures.
Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces. Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards.
Analyze firmware architecture and requirements, design requirements, and customer requirements to create implementation plans.
This role drives system definition, characterization strategies, and cross-functional execution to deliver products that meet customer, platform, and roadmap requirements.
We work at the intersection of design, technology, and manufacturing to deliver next‑generation HBM solutions that power AI and ML workloads worldwide.
This role owns next‑generation HBM core‑die architecture and critical DRAM circuit design that directly impact bandwidth, power, area, thermal efficiency, and long‑term reliability.
Signal integrity channel analysis for 2.5D and 3D silicon interposer — including frequency-domain characterization (insertion loss, return loss, PSXT, IL-to-XT ratio) and time-domain analysis (eye diagram, BER, jitter decomposition).
If you enjoy solving difficult engineering problems and influencing technical direction, you'll find plenty of opportunities to make an impact here.
As a Principal Engineer within the Validation Strategy & Test Architecture organization, you will define and drive the future of validation strategy, coverage architecture, and next-generation validation solutions for Micron's Data Center SSD portfolio.
As a Principal Pricing Analyst, you will shape pricing strategies for embedded memory solutions. You will turn customer, contract, and market data into recommendations that support competitiveness, market-share goals, and profitability.
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