Evaluate architectural trade-offs based on features, performance requirements and system limitations. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
- 5+ years experience
- Degree required
- Apply on company site
- Benefits
- Equity
- Bonus
- Health insurance
- 401(k)
- Pension
- Paid time off
- Parental leave