Act as the primary technical support for L10/L11 rack-level integration for our Original Design Manufacturers (ODMs) responsible for next-generation data center products.
Closely partner across engineering, marketing, and external partners to define and prioritize product features, enhancements, and innovations. Develop and communicate a clear product positioning for the laptop lineup.
Take charge of the strategic direction for storage products, roadmap, and requirements for DSX/DGXC to determine how storage partners connect with NVIDIA’s architecture, including APIs, reference architectures, qualification paths, and incentives for adoption.
Lead development and implementation of category strategies to optimize vendor relationships, drive cost savings, and support execution of marketing and event initiatives. Develop a global supplier catalog for Marketing and Events categories i.e.
Recruit, grow, and lead a team of TPMs running image quality programs across Jetson and DRIVE. Set priorities across the camera ecosystem portfolio, direct engineering time, and represent NVIDIA in executive-level meetings.
Own the product vision, strategy, and roadmap for training data acquisition and preparation. Translate research priorities and model capability gaps into source requirements, platform investments, and dataset acceptance criteria aligned with training schedules.
Lead cross-functional debug of critical system-level issues across hardware and firmware domains focusing on high-speed interconnects and fabrics. Perform hands-on root cause analysis of failures observed during system validation, production, or in-field operation.
Take ownership of the Infrastructure Developer Tools product strategy, roadmap, and requirements for DSX/DGXC to enable the NCP, OEM, and ISV ecosystem to left-shift software development.
Work on Thermal and Structural design of Silicon Photonic designs. Run stress simulation in optical components and fiber alignment and propose improved design of optical components.
Lead and Encourage: Drive Speed/Reliability system design and verification. Define closed loop methodologies and KPIs. Left shift faetures/methodologies to intercept design. Follow through with chip design teams by leading verification activities for Speed, Rel and Power.
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