Define technical strategy and development of NVIDIA’s Data Center diagnostic systems, orchestrating large-scale stress testing for CPUs, GPUs, networking, memory, and high-speed interconnects.
Lead and grow a high‑performing MLOps engineering group tasked with managing end‑to‑end data pipelines supporting NVIDIA’s autonomous driving technology from levels L2 through L4.
Drive the engineering contribution strategy across the JAX ecosystem stack — including JAX core, XLA, Shardy, MPMD, and application-level codebases like MaxText — prioritizing where NVIDIA's contributions create maximum impact on performance, adoption, and ecosystem influence.
Improve reliability, performance, observability, release confidence, and end-user experience across desktop, web, and service-based AI products.
Architecture Leadership: Define the long-term technical roadmap for communication libraries across NVIDIA’s next-generation platforms. You will ensure the seamless scaling of models to clusters comprising hundreds of thousands of nodes.
Setting the long-term technical vision for distributed AI communication systems—GPU-to-GPU, GPU-to-storage, and cross-node data movement. Conducting original research and prototyping next-generation networking solutions over RDMA, NVLink, and GPUDirect.
Engage closely with our AI and ML research teams to discern their infrastructure requirements and barriers, converting those insights into actionable improvements. Proactively identify researcher efficiency bottlenecks and lead initiatives to systematically improve it.
Lead end-to-end performance analysis and optimization of innovative LLM pre-training and post-training workloads on the latest NVIDIA hardware and software platforms.
Innovating and improving CPU performance through modern microarchitectural ideas. Modeling potential improvements to determine their merit and feasibility. Implementing effective solutions and collaborating closely with build, verification, and post-silicon teams.
Bridge the gap between architecture, RTL implementation, and physical design. Serve as subject matter expert on power delivery/regulators, power gating, di/dt, and thermal throttling. Analyze power trade-offs for different die stacking and packaging proposals.
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