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GenAI System Development: Design, build, and improve GenAI-powered and agentic systems supporting ASIC semiconductor engineering workflows such as code generation, data extraction, analytics, documentation automation, failure triage, root cause analysis, and technical knowledge…
Create, carry out, and refine environmental compliance programs to align with federal, state, and local requirements. Manage air, water, stormwater, natural resource permits, and spill prevention programs, including inspections and reporting.
Digital ASIC design methodology; Mixed-mode design and validation; Design or Verification CAD tools, including NCSim; Design Compiler, Formality, or PrimeTime; TCL, PERL, C, C++, or Python; and. Non-volatile memory design (NAND).
Lead and continuously improve Micron's global chemical compliance strategy, standards, governance framework, and business processes. Establish program priorities, objectives, metrics, and roadmaps that align regulatory requirements with business goals and growth strategies.
Develop and evolve Micron's corporate narrative, messaging architecture, and storytelling frameworks. Translate complex technology, market, business, and geopolitical topics into clear, compelling messaging and proof points.
Finance process and standard methodologies, such as budgeting, variance analysis and driver-based planning. Utilizing database design, development, and administration to analyze user requirements and develop logical system solutions.
1.Technical Domain Expertise (Client Computing). Strategic Marketing & Business Acumen. Product Lifecycle Management (PLM). DRAM (DDR4, DDR5, LPDDR5/5X, CAMM2) and NAND Flash (QLC/TLC, 3D NAND, NVMe SSDs).
Semiconductor device physics, MOSFET working principles, and fabrication processes; CMOS or DRAM/NAND/NOR memory reliability failure modes; Statistics and Process Control (SPC) concepts in manufacturing environment; and.
Cryptographic principles and technologies; Public Key Infrastructure (PKI) experience and related technologies; Cloud-based security solutions; Developing Python based applications in the security realm;
Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces. Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards.
Develop hardware and system specifications from architectural and product requirements. Lead PCIe bring-up, characterization, debugging, validation, and compliance activities for SSD controller SoCs.
• Define and evolve DRAM system architectures that address performance, capacity scaling, reliability (RAS), and observability requirements.
Route and qualify leads into executive-relationship or early-architecture motions with clear next steps. Improve and maintain scalable operating standards, documentation, and training. Serve as the primary contact for commercial updates, customer signals, and product offerings.
If you enjoy solving difficult engineering problems and influencing technical direction, you'll find plenty of opportunities to make an impact here.
MicronNew · 2d ago
If you enjoy solving complex technical challenges and influencing how enterprise storage products are tested, you'll find exciting opportunities here!
The Senior Director, Semiconductor Sourcing and NPI Procurement leads the global strategy, sourcing, and supplier ecosystem for wafer foundry services, IP and EDA services, discrete actives semiconductors, and 3rd party NAND flash controller categories as well as the New…
At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing.
Set Strategic Vision and Direction: Define and champion the long-term strategy for Micron’s cloud memory business, ensuring alignment with the company’s vision to transform information into intelligence and enrich life globally.
At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing.
We are seeking a motivated engineer to join the DRAM Systems Engineering team, focusing on the development, evaluation, and optimization of next-generation memory systems for AI accelerators.
Innovate and architect innovative memory/storage solution for high performance and energy efficient systems. Identify and innovate new concepts and features based on customer requirements.
This Notice is provided as a result of the filing of applications for permanent alien labor certification for the positions noted below. Any person may provide documentary evidence bearing on an application to the Certifying Officer, U.S.
Assess HBM architecture choices through layout feasibility, floorplanning, and performance, power, and area analysis. Lead custom layout and full-chip integration for analog, mixed-signal, digital, and memory blocks.
Develop hardware and system specifications from architectural and product requirements. Lead PCIe bring-up, characterization, debugging, validation, and compliance activities for SSD controller SoCs.
San Jose, USA
Munich (Leopold), Germany