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Bridge the gap between architecture, RTL implementation, and physical design. Serve as subject matter expert on power delivery/regulators, power gating, di/dt, and thermal throttling. Analyze power trade-offs for different die stacking and packaging proposals.
In this role, you will manage and help lead post-silicon bringup, characterization, and productization of the memory system for NVIDIA's GPU products. Develop, qualify, and work on compliance of memory system software and firmware.
Design and build performance analysis tools and workflows for AI training and inference workloads. Understand how AI performance engineers work and translate their needs into scalable, intuitive tooling.
Act as a trusted technical advisor for research labs, identifying and accelerating high-impact workloads by integrating NVIDIA's frameworks, libraries, and core software stack into research projects.
Lead the multi-year technical plan for AI Cloud Storage expansion across NCPs — determine the reference architecture, capabilities, performance and durability SLOs, qualification methodology, and roadmap for the high-performance file, object, and block storage that each NCP…
Set multi-generation, cross-portfolio power strategy. Own perf/watt across server-, client-, and edge-class platforms. Drive performance-versus-power analysis that influences major silicon trade-offs and product roadmap decisions. Lead silicon and vendor/IP co-architecture.
Build, develop, and maintain scalable 3D simulation software for Digital Twin and Synthetic Data Generation applications. Collaborate with multi-functional teams to build backend services and AI Agents to create end-to-end SDG solutions.
Design and architect AI/ML models—including deep neural networks, graph neural networks, transformers, and reinforcement-learning agents—for quantum error correction, syndrome decoding, logical operation synthesis, and real-time calibration in fault-tolerant quantum systems.
Build FPGA prototypes and hardware emulation environments by making RTL FPGA/emulation-friendly, partitioning the design, and taking it through synthesis, place-and-route, and emulator compilation flows.
Develop and lead incident response and disaster recovery plans for pre-production clusters. Work with infrastructure, networking, storage, OS, firmware, and application teams to harden systems. Train peers and users on practical security standard methodologies.
Build, implement, and optimize CUDA kernels for equivariant neural network primitives — tensor products, segmented polynomials, and triangle-based operations — targeting peak performance across NVIDIA GPU generations.
Accountable for managing and communicating processes, material readiness, build schedule exercises and communicating status back to the larger team in headquarter. Drive factory MP teams to efficiently and effectively check BOM/ECO implementation.
Work on NVIDIA gaming / workstation / compute GPU cards during NPI and in production.
Working closely with product engineering, lab operations, and facilities teams, this role drives the full lifecycle of MEP infrastructure that supports NVIDIA's showcase-ready lab environments—from early-stage planning and design through construction, commissioning, and ongoing…
Provide cross-functional Go-To Market (GTM) leadership to grow the vGPU software business. Define, document, and align the GTM team on sales strategies and execution.
Lead, hire, and develop software engineers within a collaborative unit; build a culture of ownership, engineering excellence, and direct collaboration with researchers and authorities in the field.
Build, implement, and optimize CUDA kernels for core MD simulation primitives. Be responsible for the end-to-end delivery of GPU-accelerated simulation math to external partners and the broader MD ecosystem. Integrate simulation primitives into major MD engines.
Design, develop, test, and optimize software for our next-generation SoCs. In both pre-silicon and post-silicon phases of execution. Review architectural performance bottlenecks for various system wide work loads.
Architect, design, develop and support tools for RTL generation across all NVIDIA products. Architect automated workflows for supporting deliverables to multiple cross functional teams.
Build and implement next-generation NvSci software to enable seamless cross-platform functionality and efficient integration with user applications, hardware acceleration libraries, and frameworks on various SoCs.
Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
Orchestrate the positioning and narrative for DSX OS components, building value propositions that connect with both technical operators and business leaders.
Lead research, development and implementation of high-volume manufacturing of high layer count PCBs. Experience with Transient Liquid Phase Sintering (TLPS) Technology or Polytetrafluoropolmer (PTFE) Materials is preferred.
As part of the product engineering group, you will handle debugging Datacenter DGX, MGX, and HGX products, focusing on identifying the root causes of factory build problems.
US, USA