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Design best-in-class SRAM circuits using state-of-the-art technology processes. Optimize circuits for performance, area, and power. Collaborate with mask designers to craft high quality and dense pitch-matched layout. Verify functionality, electrical integrity, and robustness.
Stay at the forefront of technology trends in AI Infrastructure & Agentic AI, proposing new product concepts. Define detailed product architectures, including performance, scalability, interoperability, and datacenter deployment requirements.
Building simulation frameworks for training and evaluating robot foundation models on top of NVIDIA's Omniverse platform. Partner directly with research to design, implement, and evaluate novel algorithms for robot learning.
Be responsible for the verification of ASIC design, architecture, golden models and micro-architecture of High Speed I/O controllers, like Ethernet and NVLink, at IP/sub-system levels using advanced DV methodologies such as UVM.
Develop simulation backends that enable fast, scalable evaluation of AI workloads across NVIDIA compiler stacks. Improve deep learning compiler kernel code generation and computational graph optimization using analysis based on modeled scenarios and performance insight.
Lead and develop teams of CPO and Networking Chip Equipment and Production Test engineers - setting direction, developing talent, and holding a high bar for quality and execution.
Work with architects, designers, and performance engineers to develop an energy-efficient GPU. Identify key design features and workloads for building Machine Learning based unit power/energy models.
Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner. Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them.
Lead a team of 5-10 system software engineers to drive new feature development and general support for GPU device drivers. Balance priorities among end-user, partner, OS, and chip bring-up requirements.
Build a cohesive narrative across the DSX portfolio, including facilities infrastructure, power and cooling, compute, networking, storage, infrastructure software, orchestration, simulation, models, and workloads.
Stand up and validate complete DSX-aligned software stacks on multi-node GPU systems. Capture the dependencies, configuration order, validation steps, and operational handoffs as you go.
The work here is rarely well-defined when it arrives. You will be given problems that appear to be performance gaps or power anomalies and encouraged to build a framework for solving them, not just tackle a single instance.
Develop workflows for experimental processing/analysis and numerical simulations with applications in imaging science, plasma and high energy physics, and material science.
Define the product features, capabilities, value proposition, positioning, and roadmap based on market analysis and customer feedback. Work closely with engineering to set requirements, priorities and drive integration with complementary NVIDIA software products.
Drive AI-based automotive systems from design through production, within power and performance constraints. Work with hardware teams to help shape future platforms for industry-leading power efficiency.
Own the end-to-end sensor hardware safety strategy for cameras, LiDAR, radar, IMUs and other sensors used in NVIDIA automotive systems.
Working with business users to understand their requirements, provide system solutions for sophisticated and exciting business problems.
You will own NVIDIA's RL post-training frameworks strategy: where we invest directly, where we partner upstream, and how we prioritize based on customer impact, ecosystem leverage, technical feasibility, and opportunity cost.
Define and prototype AI system architectures spanning optical and e-beam inspection, wafer and mask inspection, metrology, defect review, equipment signals, and process data.
Lead end-to-end analysis of LLM/VLM inference processes. Define representative prefill and decode workloads. Optimize time to first token, inter-token latency, P99 end-to-end latency, processing efficiency, and key-value (KV) cache capacity.
Develop and ship behavior and trajectory planning for an L4 robotaxi (lane changes, merges, intersections, unprotected turns, yielding, stop-and-go, curbside operations).
Lead petabyte-scale storage deployments across NVIDIA's on-premises data centers and major CSPs (AWS, Azure, GCP), owning the end-to-end lifecycle from design and procurement through physical installation, configuration, and production hand-off.
Engage with Researchers and ML engineers to architect and optimize end-to-end training workflows for robotics foundation models, like World Models, VLAs, WAMs.
Design and develop new features for RTOS and hypervisor software stack. Bring up and optimize RTOS and hypervisor stacks on new NVIDIA Tegra SoCs. Develop high-integrity software using best-in-class engineering, safety, and security practices.
US, USA