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Lead and Encourage: Drive Speed/Reliability system design and verification. Define closed loop methodologies and KPIs. Left shift faetures/methodologies to intercept design. Follow through with chip design teams by leading verification activities for Speed, Rel and Power.
Build validation test suites for high-speed I/Os and the analog circuits. Conduct detailed characterization of analog, digital, and mixed-signal circuit blocks across process, voltage, and temperature variations, and correlate the data with simulations.
Drive end-to-end system architecture from silicon to rack level. Lead cross-domain optimization efforts involving power delivery, thermal design, signal integrity, and mechanical constraints.
Contribute to the design of the next generation of high-speed IOs, including NVLink and NVLink-C2C. Responsible for IO power optimizations and continuing to push energy efficiency.
Develop and deliver production-quality agentic AI systems from start to finish using Python and/or Go, covering Kubernetes deployment, agent runtimes, memory systems, orchestration, tool integration, and evaluation pipelines.
Design and scale observability platforms handling high-volume metrics, logs, and traces across distributed environments. Build high-performance backend services for telemetry ingestion, processing, and routing.
Leading multi-functional initiatives to define safety architecture and requirements for autonomous vehicles. Delivering safety concepts and analysis to enable continuous and safe software deliveries.
Define technical strategy and development of NVIDIA’s Data Center diagnostic systems, orchestrating large-scale stress testing for CPUs, GPUs, networking, memory, and high-speed interconnects.
Lead and Inspire: Manage, mentor, and scale a high-performing organization of engineering managers, applied researchers, and software engineers dedicated to autonomous vehicle perception.
Serve as a technical advisor and problem solver with partner engineering teams, collaborating on architecture, code, and integration for Omniverse and AI enabled-solutions.
Design, build, and maintain analytics-focused data pipelines that ingest, transform, and curate observability data from EDA datacenters. Develop reliable ingestion pipelines for metrics, logs, traces, and hardware health telemetry generated by large-scale CPU and GPU clusters.
Design, build, and maintain analytics solutions across the full lifecycle from data ingestion to reporting and Databricks-hosted application delivery.
Address customer and partner optimization challenges: Engage directly with prominent automotive OEMs and robotics associates to analyze, debug, and improve their deep learning models on NVIDIA platforms. We emphasize delivering solutions rather than just recommendations.
Design and build robust and accurate solutions for map enhanced autonomous driving with ASIL safety requirements in mind. Localize to map data to provide the most precise and rich model of the environment around the car, including beyond the horizon of perception.
Define and develop metrics that enable rapid debugging, testing, and evaluation of our Autonomous Vehicle software. Build compelling, data driven evaluation products by combining on-road driving analysis, large scale simulation, models, metrics and dashboards.
In this role, you will research and develop techniques to accelerate top CSP workloads on NVIDIA’s computing platform including advanced CPUs, GPUs and interconnects.
Work on crafting creative Signal Integrity solutions to complex system design problems. Modeling and Optimization of vias, connectors, sockets, breakouts and various system components in 3D EM tools.
Architect end-to-end reference architectures for disaggregated inference (aligned with NVIDIA Dynamo), large-scale foundation model training, and agentic AI pipelines — co-developed with storage and ecosystem partners.
Develop new approaches and implement improvements to existing algorithms for sensor calibration for ADAS using both classical and deep learning methods.
Participate in ground breaking processor design in deep submicron technologies. Work as part of a global circuits team to design innovative circuits for hardware security, adaptive clocking, and power management solutions.
Design high frequencies channels up to 400Gb/s per lane for PCBs, packages, connectors and cables. Design layout guidelines for NVIDIA systems. Simulate passive and active elements in 3D and 2D simulation tools.
As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip. Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation.
Lead and grow a high‑performing MLOps engineering group tasked with managing end‑to‑end data pipelines supporting NVIDIA’s autonomous driving technology from levels L2 through L4.
Managing a team of experienced compiler and performance engineers. Establish team objectives to meet schedules and goals. Act as a mentor and advisor to grow our next generation of leaders. Establish and evolve policies and procedures that affect the immediate organization.
US, USA