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Lead communications with internal clients and other cross-functional teams to help flesh out the project scope, including campaign objectives, strategy and insights, deliverable requirements, and metrics.
Representing NVIDIA’s functional safety strategy and architectures to the customer. Working closely with customers to understand their functional safety requirements and system architectures and feeding those back into the development teams.
Lead system-level power failure analysis for customer returns and field failures across data center systems, compute trays, and compute modules.
Invent new methods to enable parallel, graph-based RTL traversal, analysis, and manipulation. Devise strategies for rapidly analyzing the impact of RTL changes on data path latency, power, and impact to DFT, clocking, and power delivery.
You and your teammates will own every part of the engineering mission of cuEST - from idea to shipped CUDA-X library.
Participate in innovative Processor design in deep submicron technologies. Work as part of a global circuits team to design innovative power delivery and power management solutions.
Work on Thermal and Structural design of Silicon Photonic designs. Run stress simulation in optical components and fiber alignment and propose improved design of optical components.
Lead a group of engineers and provide technical guidance and career mentorship to the team of highly skilled engineers. Empower the team members to excel and increase team productivity.
We support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches).
Define and implement the technical vision and strategy for next-generation developer tools, workflows, and technologies that improve developer productivity. Design and prototype new tools that can evolve into production-ready software.
On this team, the goals and objectives are carried out through a high degree of collaboration and use of state-of-the-art methods and technologies, analytical and computational analysis, and laboratory validation.
Drive development and productization of NVIDIA’s DGX and MGX datacenter products and L11 systems. Lead debug efforts for L11 rack-level integration, creating and applying tools/scripts for failure identification and root cause analysis.
Define, design, develop and verify features for next-gen RISCV controllers on our GPU; collaborating with hardware engineers and fellow software engineers.
Create new and innovative prototypes that test future capabilities, build experience with technologies required for future products, and guide integration for mass production.
Support the development and documentation of product requirements for high-speed cables and connectors. Collaborate with senior engineers and cross-functional teams to understand customer needs and translate them into design inputs.
Lead signal integrity design and analysis for high-speed SerDes channels across die, package, board, connector, socket, and cable interfaces.
Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs.
Run AI factory validation tools, microbenchmarks, and workloads provided by the team, and interpret results to assess system health and performance. Gain a comprehensive understanding of the system from start to finish, including network topology, interconnects, and compute.
In this role, you will be working on CUDA Tile, a new tile-based programming model for our GPUs. CUDA Tile shipped with CUDA 13.1 and is a major addition to CUDA (https://developer.nvidia.com/cuda/tile).
NVIDIA · 14d ago
Lead end‑to‑end performance and scalability analysis across the Kubernetes‑based accelerated runtime stack (control and data planes), including NVIDIA components such as GPU Operator, Network Operator, node-feature-discovery, topograph, dra-driver-nvidia-gpu, and nvsentinel,…
Define high-level SoC subsystem architecture for LPU products. Convert LPU product requirements into architectural specifications for uncore, IO, memory, firmware-facing, boot, reset, safety, fault tolerance, diagnostic, and power regulation subsystems.
Own APF Core Services: Build and harden the Runtime Policy Verifier, signed policy bundle verification, trust-root handling, freshness, rollback protection, subject binding to attested runtime context, revocation checks, and authorization APIs used by APF-compatible enforcement…
Provide Technical Leadership to the team of Data Scientists and Engineers working on global deployment at scale of GPU Compute services.
Own positioning and messaging for CUDA Python and CUDA Rust, translating compiler and programming-model capabilities into crisp developer narratives, release messages, proof points, and field-ready assets. Support CUDA C++ messaging as needed.
US, USA