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Architect and integrate system-level performance and power management features, controllers, and policies to optimize product efficiency across datacenter and client products .
You will be the Point of Contact and own the SDLC for the programs, ensuring the highest quality of software deliveries. Define technical direction, breakdown, and be the quality bar for NVLink features, and drive them from idea to production as a hands‑on IC.
Lead bring-up, validation, and debugging of large-scale AI clusters, infrastructure, and end-to-end workloads, setting the standard for how the team operates.
In this role, you will: Work alongside our senior leadership to offer counsel on challenging HR topics, organizational frameworks, and talent strategy.
Hands-on leadership of HBM/GDDR enablement, validation, and failure analysis for NVIDIA’s datacenter and graphics products. Drive review of memory partner’s design limits and test methodology.
Module and board NPI for datacenter and HPC products is the core of this role — from first-article through mass production ramp, with accountability for yield targets, quality gates, and on-time delivery.
Define the comprehensive test development strategy across wafer-level (probe/ATE) and package/final/qual test for new and existing product families. Lead architectural trade-off decisions on test coverage, test time, cost of test, and quality escapes across the full test flow.
Own system architecture for inference stack and other applications running on this class of products and make it resilient to any fault happening in space.
Characterizing AI workloads and deep learning models aimed at large-scale LLM training and inference on NVIDIA supercomputers. The role centers on distributed systems with a focus on high-performance networking and NVIDIA communication libraries.
Play a key role in design, development, and deployment of AI applications using LLMs, internal and external Agentic frameworks, and other related technologies.
Develop scalable simulation platforms and workflows for autonomous driving validation and training.
As a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks.
Build synthetic data generation pipelines using LLM-based methods and automated quality evaluation, producing datasets that improve the pre- and post-training of LLMs such as Nemotron — reasoning, coding, structured output, and multimodal understanding.
Research and develop open AI models for quantum system calibration to advance the state of the art and empower the quantum community to build on shared foundations.
Own the SoC-level verification plan, schedule, and achievement tracking from the conception of project through tape-out, serving as the primary PIC across all verification workstreams.
While engaged in frontend development, your responsibilities will include working on a wide range of high-speed, powerful DSPs, silicon photonics IPs, and chips. You will participate in chip-level features, programming model and application interface definitions.
Support the planning, development, and execution of coordinated semiconductor campaigns, from major launches to sustained engagement programs.
Own end-to-end product validation from architecture/design phase, through bring-up to mass production: set strategies, define test plans, and track progress to ensure the product meets spec and ships successfully. Lead and mentor design validation engineers.
Identify, develop and close strategic design wins for DPU and SuperNIC solutions with lighthouse AI labs and hyperscaler AI infrastructure customers.
Drive architectural specifications to closure across multiple stakeholders. Develop written specifications for key component-level and system-level designs. Embody specifications in an executable model used by many customers across NVIDIA.
Develop cybersecurity campaign strategy that will transform complex technologies into compelling, audience-first narratives. Hands-on execution, with cross-team collaboration, of all beat moments (product launches, ecosystem activations) as well as sustained engagement programs.
As a member of our team, you will collaborate with multi-functional teams to drive the silicon validation of NVIDIA's chips. In this role you will drive the end to end DFT architecture and methodologies to accelerate the post silicon bring up & characterization.
Designing, implementing, and optimizing direct sparse solvers for existing and future GPU architectures. Working with library engineers, QA engineers, and interns on all library development aspects from design to implementation and test to release and support.
Work on the cutting edge standard cell libraries and/or custom ROM (Read Only Memory) modules in deep submicron technologies. Drive the concepts of the transistor level standard cell circuit design, modeling and performance analysis process.
US, USA