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Define ICT capability, hardware design requirements, and board debug capabilities, enabling structural testing at Texas CM sites. Optimize structural test plans to identify SMT, PCB, and component issues early.
Own the technical vision, architecture, and roadmap for 3D obstacle perception to support end-to-end autonomous driving functionalities, leveraging state-of-the-art CNN and transformer-based architectures where appropriate.
Own board and system level hardware reliability across NVIDIA's product lines, including Data Center, Server, Graphics Cards, Automotive, Embedded, and emerging platforms.
Develop, validate, and release PCB footprints, padstacks, schematic symbols, panel definitions, and mechanical library content using Cadence Allegro and related design tools.
Research and propose novel transport mechanisms based on RDMA technology for AI systems using simulations, experiments and proof-of-concept prototypes. Architect the frameworks for NVIDIA’s programmable networking devices for novel protocols.
Track the cutting edge: How are agentic systems evolving? You'll follow research in tool use, planning, memory, evaluation, self-improvement, multi-agent workflows, runtime infrastructure, and agent safety/security.
Learn and apply formal verification techniques to real processor and accelerator designs. Understand design behavior from specifications, RTL, and discussions with design teams. Write assumptions, assertions, and cover properties to verify important microarchitectural behavior.
The team is responsible for developing high performance communication frameworks and applications running in production on the world’s largest supercomputers and datacenters.
First and foremost, you will be the key point person for all things robotics training data: requirements gathering, data collection, quality assurance, partner discussion, and data impact evaluation.
Collaborate across the company to guide the direction of platform security and develop a long-term roadmap for a flexible HW Root of Trust solution that will be integrated into our products, working with hardware, software, research and marketing teams.
Design and evaluate routing policies for LLM traffic to best use mixture of model systems. Build and run agentic benchmarks (e.g., Terminal-Bench ) to measure algorithm quality, and turn results into calibration data and routing profiles.
Provide onsite support for large datacenter deployments of NVIDIA AI solutions. Solving complex hardware and deployment issues.
Develop verification infrastructure (testbenches, BFMs, checkers, monitors, randoms). Come up with, review and drive test plan execution for planned features. Understand the performance requirements of your IP, come up with, review and drive performance testplan for your IP.
Support networking technologies such as Spectrum-X and work with customers on their technical challenges and requirements using said technologies during pre-sales activities. Develop proof-of-concept materials for innovative technologies for use by early adopters.
Design, develop, and verify features for next-generation GPU driver architecture in close collaboration with hardware and software engineering teams.
As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. Analyze architectural trade-offs based on features, performance requirements and system limitations.
Lead a team of Product Reliability Engineers. Drive end-to-end reliability strategy throughout the product lifecycle (concept → qualification → production → field). Coordinate the creation and implementation of the reliability test plan.
Modeling and analysis of SoC & Systems algorithms and features. Work in a matrixed environment, across the different modelling teams, to document, design, develop tools to analyze and simulate, validate, and verify models.
As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products.
Lead the Isaac Manipulation team. Recruit, grow, and mentor a high-performing team of robotics software engineers; set direction, raise the technical bar, and manage the team’s health, velocity, and delivery.
Drive, execute and deliver forecasting, planning and analytics relevant to the company’s financial calendar. Develop ownership of product margin analytics across the Graphics stacks.
Advanced Analytics: Apply quantitative and qualitative analysis to identify problems, develop hypotheses, and recommend data-backed solutions for compensation programs and processes.
As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas.
You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF…
USA