Every listing shows a published salary. Filter by role, country, remote work or seniority. Updated 16h ago.
Develop infrastructure software and tools for large-scale pre-training, post-training, and inference. Develop and optimize tools and libraries to improve infrastructure efficiency and resiliency. Co-design and implement APIs for integration with NVIDIA's resiliency stacks.
Working on backend and frontend design and development of web applications targeting VLSI design and modeling. Collecting requirements and provide consultation to end users about their needs and use cases. Analyzing performance bottlenecks.
Drive the software end-to-end architecture for NVIDIA's rack-scale products. Maintain deep understanding of the product portfolio and roadmap; translate forward-looking plans into clear, formal software requirements that anchor execution across the organization.
Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency. Working with other design teams to define interfaces and flows between NVLink C2C blocks and the rest of the chip.
The role entails working collaboratively and multi-functionally with a multi-disciplinary team of Circuit designers and mask designers.
Partnering with MEM suppliers to conduct process improvement efforts involving engineering data examination. These efforts include device optimizations, detailed process weakness improvements, electrical test analyses, and process and Fab qualifications.
Build, develop, and maintain high-performance runtime and compiler components, focusing on end-to-end inference optimization. Define and implement mappings of large-scale inference workloads onto NVIDIA’s systems.
NVIDIA · 14d ago
Build, develop, and maintain high-performance runtime and compiler components, focusing on end-to-end inference optimization. Define and implement mappings of large-scale inference workloads onto NVIDIA’s systems.
Diagnosing GPU and CPU performance bottlenecks in Vulkan and Proton titles. Identifying changes to API usage to improve performance and communicating via appropriate channels with third-party developers. Implementing driver performance improvements and resolving driver defects.
Support new supercomputers and AI fabrics technologies. Gain our customers’ trust and understand their needs. Work closely with various R&D teams and develop features for our customers. Lead the way on cooperation’s between different teams within the company.
Identify key behaviors for verification to write clear testplans for sophisticated designs. Implement testplans using the latest formal techniques, including the development of environment assumptions, assertions, and cover properties.
Research, design, and implement novel, large-scale generative AI methods. Publish original research. Collaborate with team members, research teams, as well as product teams. Speak at conferences and events. Transfer technology to product groups.
Collaborate with software engineers, hardware and architecture teams to design, develop, integrate, validate, and optimize software on NVIDIA's DRIVE self-driving platform.
Main task: Verify AI-related sophisticated ASIC designs & features with formal verification methods. Multi-functional Collaboration: Partner with architecture/RTL teams to specify properties, resolve deep design issues, and influence micro-architecture decisions.
Our team owns, develops and delivers the Manufacturing, Test, and Failure Analysis/recovery process for new datacenter servers and assemblies incorporating the latest NVIDIAs GPU, CPU, and high speed interconnect technologies.
As a Senior Design Engineer at NVIDIA, you will be responsible for the development and micro-architecture of a high-performance MMU for a GPU using advanced verification methodologies. Contribute to architecture decisions. Mentor other engineers on the team.
Architect, design, develop and support tools for RTL generation across all NVIDIA products. Architect automated workflows for supporting deliverables to multiple cross functional teams.
Main task: Verify AI-related sophisticated ASIC designs & features with formal verification methods. Multi-functional Collaboration: Partner with architecture/RTL teams to specify properties, resolve deep design issues, and influence micro-architecture decisions.
Research, design, and implement novel, large-scale generative AI methods. Publish original research. Collaborate with team members, research teams, as well as product teams. Speak at conferences and events. Transfer technology to product groups.
Define and conduct original research across EDA algorithms, VLSI design methodology, and advanced AI techniques.
Architecting and maintaining custom profiling frameworks that provide a unified view of execution across CPU (multi-core/multi-socket) and GPU (multi-node/NVLink) environments.
As a Senior TPM, you will bridge the gap between architectural concepts and physical silicon. Your mission is to accelerate tape-out cycles by optimizing engineering workflow schedules and to track Closed-Loop Validation.
NVIDIA · 14d ago
Develop world-class GPU-accelerated AI inference serving software. Contribute to feature development and drive broad customer adoption. Drive the convergence of the Triton Inference Server and NVIDIA Dynamo stacks to establish a unified, high-performance inference platform.
Develop and execute verification plans for SerDes digital designs, golden models, and microarchitecture using SystemVerilog/UVM, simulation, and hardware emulation.
US, USA
Canada, Canada