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Own and drive the definition, planning, and execution of verification strategies for sophisticated CPU designs. Apply brand new verification methodologies and techniques to improve efficiency and ensure continuous improvement in CPU verification.
Lead end-to-end execution for data-center power architecture programs, including Power Shelf, BBU/CBU, busbars, and other rack-level power components.
Design novel GPU and system architectures to advance the forefront of AI Inference performance and efficiency. Construct, investigate, and test popular deep learning algorithms and applications.
Guide the design and implementation of a new LLVM-based backend JIT compiler targeting NVIDIA GPUs. Design and develop new compiler passes and optimizations required to meet the high-performance and low compilation time requirements of the compiler.
Architect next generation power management features and solutions, through system architecture, design, and productization; working with multi-functional teams across the company.
As a key member of our ASIC Verification team, you will verify the design and implementation of inference accelerator. You will be responsible for verification of the ASIC design, architecture, reference models and micro-architecture using advanced verification methodologies.
NVIDIA · 14d ago
Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.
In this role, you will research and develop techniques to accelerate large scale applications running on NVIDIA’s family of advanced CPU platforms.
Collaborate with major cloud service providers (CSP), their OEM/ODM’s, and internal teams to help deploy the latest NVIDIA Vera-Rubin AI rack’s.
Install, configure, and support foundry techfiles. Perform expert debug of design errors to direct expeditious resolution: explaining user errors to designers; explaining techfile errors to the foundry support team, and explaining tool errors to EDA partners.
Modeling of GPU architecture, baseboard components and other features. Work in a matrixed environment, across the different modeling teams, to document, design, develop tools to analyze and simulate, validate and verify models.
Analyzing deep learning networks and developing compiler optimization algorithms. Collaborating with members of the deep learning software framework teams and the GPU architecture teams to accelerate the next generation of deep learning software.
Implement, enhance, optimize, and deploy new tools for chip level placement, reshaping and route optimization. Create innovative algorithms for computational geometry, placement, fast routing etc. to efficiently arrange the blocks in a chip.
Coordinate equity processes for globally mobile employees to support compliance and reporting requirements. Support RSU vesting activities, including coordination with Payroll and Finance teams.
Subject matter expertise in government and/or grant compliance including applicable regulatory frameworks, i.e., Federal Acquisition Regulations (FAR), Cost Accounting Standards (CAS), DFARs, Uniform Guidance, Service Contracts Act, etc. and general contracting and pricing…
Working with NVIDIA multi-functional teams for notebook feature development, Build design guides, application notes and other supporting technical collateral for notebook. Provide technical support during notebook development, testing, and production.
Participate with partners on diverse long-haul terrestrial routes to ensure network resilience and high-capacity data flow between regional AI hubs. Participate in subsea and terrestrial consortiums to enable capacity, efficiency, and optimize cost-per-bit for transit.
Developing co-marketing plans with our ISV that generate awareness, thought leadership, and demand for our Enterprise platforms. Enabling and supporting the execution of such marketing plans with partners.
Develop use cases and system requirements for L3 and L4 autonomous driving products based on customer needs, traffic regulations, certification standards, and industry guidelines.
Develop innovative high-performance processor and system architectures, focusing on the memory system and energy efficiency.
Guide the design and implementation of a new LLVM based backend JIT compiler targeting NVIDIA GPUs. Design and develop new compiler passes and optimizations required to meet the high performance and low compilation time requirements of the compiler.
Lead architecture discussions with customers and co-design scalable inference systems with product and engineering teams. Define technical direction, integration milestones, and deployment plans across edge and cloud environments.
Develop innovative high-performance processor and system architectures, focusing on the memory system and energy efficiency.
Lead software integration with a systematic approach to streamline embedded development for NVIDIA Drive Autonomous vehicle solution products.
US, USA
Canada