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Work closely with LLVM, Clang, MLIR, and related open‑source communities to upstream compiler features, refactors, and infrastructure originating from NVIDIA’s downstream codebases.
Design and maintain teleoperation software for controlling humanoid robots with low latency and high precision; Develop and optimize the control stack, including locomotion, manipulation, and whole-body control algorithms;
As a Senior Photonics Layout Engineer, you will take ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs), guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness.
Develop full-system functional models capable of running complex multi-threaded heterogeneous (CPU/GPU) workloads – with special focus on the CPU subsystem.
Driving the evolution of CAD and PLM ecosystems to support rapid, high-fidelity hardware iteration across the enterprise. Architecting data-driven workflows and analytics platforms that provide real-time insights into system design health and project achievements.
Architect multi-GPU system topologies for scale-up and scale-out configurations, balancing AI throughput, scalability, and resilience. Define, modify and evaluate future architectures for high-speed interconnects such as NVLink and Ethernet co-designed with the GPU memory system.
In this position, you will be responsible for verification of high-speed coherent interconnect design, architecture and golden models. You will be responsible for micro-architecture using sophisticated verification methodologies.
Develop and maintain strong technical proficiency in capital markets workflows, including quantitative research, trading systems, risk analytics, and market data pipelines.
As a core contributor to the CUTLASS project, you will use your expertise in systems programming and API design to create a world-class developer experience for GPU programming and kernel delivery.
We are looking for a highly skilled Performance Modeling Architect to lead the architectural definition and improvement of our next-generation CPU Cache Hierarchies and interconnects.
Draft and refine high-impact communications for senior leaders, including speeches, fireside chats, remarks, talk tracks, Q&A, briefing sheets, and follow-up content.
Build FPGA prototypes by taking the design through synthesis and place and route, analyzing timing and generating bitstreams. Bring up the design on FPGA prototyping platforms involving hands-on lab debug with HW and SW debuggers.
Define and implement tools and methodologies for efficient data generation from post layout netlists to feed into data movement power analytical model. Develop tools and infrastructure to sanitize each metric in the model to achieve high correlation accuracy.
Participate in every facet of the definition, positioning, architecture, and execution of GPU and SoC-based products. Fields include but not limited to automotive, robotics, industrial PC, consumer electronics, medical devices, etc.
Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis,…
Investigating the latest and future NVIDIA GPU hardware architecture and programming models.
Program Lifecycle & Strategy: Lead end-to-end data programs from acquisition through release. Translate machine learning research requirements into sourcing plans and drive cross-functional alignment between engineering, legal, and operations to meet program milestones.
Planning, coordinating, and tracking manufacturing progress to the stated program goals. Collaborating with Engineering and Diagnostics teams to coordinate product Firmware and test diagnostics upgrades.
Design and implement simulation infrastructure using C++, SystemC, and Transaction Level Modeling. Develop solutions for scheduling, concurrency, communication, and synchronization across simulation processes and kernels.
We need someone who will design, develop, and maintain circuit design and verification flows that run on large‑scale compute and GPU farms located across geographies through various job schedulers.
Bridge the gap between architecture, RTL implementation, and physical design. Serve as subject matter expert on power delivery/regulators, power gating, di/dt, and thermal throttling. Analyze power trade-offs for different die stacking and packaging proposals.
In this role, you will manage and help lead post-silicon bringup, characterization, and productization of the memory system for NVIDIA's GPU products. Develop, qualify, and work on compliance of memory system software and firmware.
Design and build performance analysis tools and workflows for AI training and inference workloads. Understand how AI performance engineers work and translate their needs into scalable, intuitive tooling.
Act as a trusted technical advisor for research labs, identifying and accelerating high-impact workloads by integrating NVIDIA's frameworks, libraries, and core software stack into research projects.
US, USA
Canada, Canada